Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit.
The above-incorporated parent applications describe a variety of means for producing substrates having conductors embedded beneath the surface of the substrate. The techniques disclosed therein provide increased conductor density and decreased inter-conductor spacing via embedded circuit technologies.
In particular, substrate and method embodiments described in the above-incorporated patent applications, a plating or paste screening process is used to provide conductive material within channels formed in a substrate. The metal is generally plated to completely fill the channels, which generally include channels forming lands for solder ball attach, passive-component attach and/or semiconductor die attach. The metal is then planarized to isolate the conductors by removing the conductive material that is above the substrate surface, forming a circuit pattern that is embedded beneath the surface of the substrate. An etching process that removes the conductive material above the surface of the substrate is one of the planarization process options disclosed in the above-incorporated parent applications.
However, when a plating process is used to deposit the conductive material in the channels and/or when an etching process is employed to planarize the conductive material, variations in width of conductors, and in particular the size of lands affects the plating and/or planarization process, as the rate of conductor deposit or removal is directly related to the size of a feature. With respect to interconnect lands, which are typically circular for a solder ball or flip-chip attach land and square or rectangular for a surface mount (SMT) component package attach land (such as lands for attaching SMT resistors, capacitors, diode and transistors), the relatively large size of the land leads to a “dimpling” effect, in which a higher etching current density around large features increases the rate of material removal. The result of the increased removal rate is a “dimple” in the centers of larger features, and in extreme cases, a loss of conductive material in the center of the feature. In the case of plating processes used to deposit the channel material, larger features lead to increased material build-up that is uneven and can result in the inability of the planarization process to remove the excess deposits.
Any of the above dimpling effects are undesirable, as the attachment region provided by the land becomes non-planar, which can affect solderball height for solderball attach lands, and planarity of SMT mounting lands. Variations in solderball height and planarity of SMT mounting lands can cause missed or weak interconnects to the substrate, resulting in failure of a circuit module.
Further, subsequent to the etching process, a further plating process is typically employed to provide improved solderability and/or protection of lands from environmental conditions such as oxidation by depositing gold or gold-nickel plating on the lands. The larger area of conductive features on the substrate such as the lands described above, increases the amount of plating material, which raises the cost of the plating procedure.
Therefore, it would be desirable to provide substrates having improved land planarity and a method of manufacturing the substrate, that reduce or eliminate the dimpling effect. It would further be desirable to provide a lower cost substrate and method of manufacturing the substrate that reduces plating costs.